By Kingshuk Karuri, Rainer Leupers
This e-book presents an outline of the hot developments in innovative layout automation instruments for program particular Instruction-set Processor (ASIP) improvement. ASIPs have gotten more and more universal in lots of embedded System-on-Chip architectures because of their special mixture of flexibleness and performance/energy potency. even if, the excessive improvement attempt linked to ASIPs has to date hindered their common recognition within the embedded international. This e-book introduces readers to a unique layout method that may considerably lessen the ASIP improvement attempt via excessive levels of layout automation. the main parts of this new layout technique are a robust program profiler and an automatic instruction-set customization software which significantly lightens the load of mapping a goal embedded program to an ASIP structure within the preliminary layout phases. The publication contains a number of layout case reviews with sensible embedded purposes to illustrate how the method and the instruments can be utilized in perform to speed up the final ASIP layout process.
- Provides a radical survey of ASIP layout regularly, and alertness research (profiling and instruction-set customization) in particular;
- Introduces a number of unique concepts/tools, in addition to algorithms and software program architectures, to let readers to construct related ASIP improvement device flows from scratch;�
- Includes case reports that systematically exhibit how ASIPs will be equipped utilizing software research instruments offered within the ebook. �
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Additional info for Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization
Hardware branch prediction is a scheme which is not commonly found in embedded architectures, although high performance general purpose processors often use it. Branch prediction significantly complicates the pipeline implementation and is not suitable for data dominated embedded applications. 3 Instruction and Data Parallelism In order to meet the stringent performance and power efficiency requirements of most portable consumer electronic gadgets, SoC designers usually try to exploit any form of available parallelism in the target applications.
5b), added in parallel using the SIMD add operation ( 4 ), and stored back to memory using a normal memory write operation( 5 ). The SIMD add has very little hardware overhead, because the four 8 bit adders can be implemented simply by deactivating the carry path of the normal 32 bit adder at the 8 bit sub-word boundaries. This example clearly demonstrates why SIMD instructions are so attractive for embedded ASIP architectures. SIMD and VLIW are complementary paradigms for exploiting fine-grained, intra-task parallelism in programmable architectures.
Interested readers may consult the classic compiler construction text by Aho, Sethi and Ulman  for a detailed treatment of the front-end design issues. However, for ASIPs, the back-end optimizations have a higher relevance. The standard compiler back-end for any processor – embedded or otherwise – consists of three phases – instruction selection, register allocation and instruction scheduling. Instruction selection converts the IR representation of an application to a sequence of processor instructions, register allocation maps program variables to processor registers, and instruction scheduling reorders the sequential instruction stream so as to avoid pipeline hazards and maximize parallelism.
Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization by Kingshuk Karuri, Rainer Leupers