By Ricardo Martins, Nuno Lourenço, Nuno Horta
This ebook introduces readers to quite a few instruments for analog format layout automation. After discussing the location and routing challenge in digital layout automation (EDA), the authors review quite a few computerized structure iteration instruments, in addition to the newest advances in analog layout-aware circuit sizing. The dialogue comprises diverse tools for automated placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The options and algorithms of the entire modules are completely defined, permitting readers to breed the methodologies, enhance the standard in their designs, or use them as place to begin for a brand new device. all of the tools defined are utilized to useful examples for a 130nm layout procedure, in addition to placement and routing benchmark sets.
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Extra info for Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
This work, AIDA-L Lopez [100, 101] Berkol  Habal  Automatic electromigrationaware WT and global routing in-loop Procedural generator (design space sampled only) Exhaustive setup Enumeration of for Cadence Chip all possible Assembly Router® floorplans Coded Template-based slicing-tree Layout description script Ranjan  Youssef  Template-based Placer with multiple B*-trees Procedural generator (design space sampled only) Template-based/ Channel router user-assisted Device-level procedural generator Pradhan  Liao  Placer Router Procedural generator Work Vancor.
Slicing tree/ polish  Slicing (+) Smaller solution space than absolute; (+) Moves are modifications in the relative positions of the cells, avoiding illegal overlaps; (−) Proximity constraints barely supported and often weighted in the single-objective cost functions. , no packing, structural scan or post-processing time is required; (−) Allow illegal overlaps during moves; (−) Slower due to the solution space infinitely large. 1 Placement 19 of placements with different aspect ratios for the whole circuit, resultant from the exploration of the tradeoff placements’ width versus height, is obtained.
Without actually generating the layout in real-time, in  device parasitic effects are modeled by linear regression from a Pareto optimal surface, obtained by sampling the design space and using a procedural generator to produce the layout for each point, where each solution is aware of its specific layout induced effect. In  the layout is also produced by a parameterized generator, where layout parasitics and devices sizes are passed to the precompiled symbolic performance model that estimates the circuit performance for each sizing solution, attempting to avoid circuit simulation.
Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques by Ricardo Martins, Nuno Lourenço, Nuno Horta