By R. Joobbani
Routing of VLSI chips is a crucial, time eating, and tough challenge. the trouble of the matter is attributed to the big variety of usually conflicting elements that have an effect on the routing caliber. conventional innovations have approached routing by way of ignoring a few of these elements and implementing pointless constraints so one can make routing tractable. as well as the imposition of those regulations, which simplify the issues to some extent yet even as lessen the routing caliber, conventional techniques use brute strength. they generally remodel the matter into mathematical or graph difficulties and entirely forget about the categorical wisdom concerning the routing job that may vastly aid the answer. This thesis overcomes many of the above difficulties and offers a method that plays routing on the subject of what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this quarter, it doesn't impose pointless constraints, it considers all of the various factors that have an effect on the routing caliber, and most significantly it permits consistent person interplay through the routing approach. to accomplish the above, this thesis provides heritage approximately a few consultant ideas for routing and summarizes their features. It then experiences intimately different elements (such as minimal sector, variety of vias, cord size, etc.) that impact the routing caliber, and the several standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.
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Additional resources for An Artificial Intelligence Approach to VLSI Routing
Later on, in Chapter 4, the reason for its failure is described and a solutionis given. 16 o o o o o o o o o o o o (a) o o o ~ o (~ o '"' (~ o ~ o ~ ) - o '"' o 0 0 L'< ~ o o ~ ( ( (~ '"' ,... ~ ~ , " (b) Figure 2·12: (a) Possible cases for a 2x2 grid with a total of 3 pins, (b) possible pat1erns for connecting 3 pins in a 2x2 grid. 4. Characteristics of previous approaches This section describes some of the common characteristics of the above, and most other existing routing algorithms. These characteristics include: 1.
It has been proved that the general problem of constructing Minimal Rectilinear Steiner Tree (MRST) is an NP·complete problem [Even 79, Garey 77a, Garey 77b, Cockayne 70]. However there are some efficient special case algorithms [Aho 77, Hwang 78] for constructing MRST which are discussed in the next section. Also presented is an algorithm which uses geometric properties to reduce the number of possible alternatives for a mxn grid. 2. Minimal Rectilinear Steiner Tree for a 2xn grid This special case algorithm [Aho 77] finds MRST for a set of points (pins) which are a subset of the grid points of a 2xn grid.
Wire length Ordering of nets based on the wire length is the easiest starting criteria and the one used by human designers. The wire length is initially measured as the differences between the number of pins of a net located on the opposite sides of a channel. The more pins a net has on the bottom/top the closer to the bottom/top of the channel the net should be routed. For example in Figure 3-5 nets 3 and 8 are routed close to the bottom and nets 10 and 4 are routed close to the top because they have the most number of pillS on the bottom and top respectively.
An Artificial Intelligence Approach to VLSI Routing by R. Joobbani